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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:27:09 05/26/2012 
-- Design Name: 
-- Module Name:    ClockGenerator - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.faw_types.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ClockGenerator is
Port ( 	clk_in : in  STD_LOGIC;
			clk_true : out STD_LOGIC;
			clk_false : out  STD_LOGIC);
end ClockGenerator;

architecture Behavioral of ClockGenerator is

begin

processo: process(clk_in)
	variable CLK_TRUE_VAR : std_logic;
	variable CLK_FALSE_VAR : std_logic;
	
	begin
	
		if (clk_in'event) then
			CLK_TRUE_VAR:=clk_in;
			CLK_FALSE_VAR:=not clk_in;
		end if;
			clk_true<=CLK_TRUE_VAR;
			clk_false<=CLK_FALSE_VAR;
		
	end process processo;

end Behavioral;

